According to common semiconductor device manufacturing techniques, multiple semiconductor elements are formed into a matrix on a semiconductor substrate such as a silicon wafer, and the semiconductor substrate is cut along scribe lines, so that semiconductor chips having respective individual semiconductor elements formed therein are obtained as semiconductor devices.
In such semiconductor devices (chips), semiconductor layers, insulating layers, and metal layers are exposed at their sections. Therefore, it is common to form a moisture resistant ring having the same layer structure as that of a multilayer interconnection structure in the semiconductor devices in the vicinity of the sections in order to prevent atmospheric moisture from entering the semiconductor devices through the sections.
FIG. 1 is a plan view of part of a semiconductor device formed on a semiconductor substrate according to the related art of the present invention. FIG. 2 is a cross-sectional view of part of the semiconductor device including a moisture resistant ring.
Referring to FIG. 1, device regions 11A, 11B, 11C, and 11D are separated by scribe lines indicated by single-dot chain lines on a semiconductor substrate. The device regions 11A, 11B, 11C, and 11D include circuit regions forming their respective semiconductor devices inside moisture resistant rings 12A, 12B, 12C, and 12D, respectively. In the case illustrated in FIG. 1, a circuit region (CKT) 13 is formed in the device region 11A. A similar circuit region is also formed in each of the other device regions 11B through 11D.
Further, according to the configuration of FIG. 1, protection groove parts 14A through 14D are formed in the device regions 11A through 11D, respectively, outside the corresponding moisture resistant rings 12A through 12D and inside the scribe lines indicated by single-dot chain lines, in order to block propagation of cracks at the time of scribing.
The individual semiconductor devices are separated in the form of semiconductor chips by cutting the silicon substrate along the scribe lines indicated by single-dot chain lines in the plan view of FIG. 1.
FIG. 2 is a cross-sectional view of a semiconductor device 10 thus obtained.
Referring to FIG. 2, the semiconductor device 10 is formed on a silicon substrate 15 where isolation regions 151 and a transistor 15Tr are formed. The transistor 15Tr is covered with a SiN film 17A. A multilayer interconnection structure of alternate layers of interlayer insulating films 16A, 16B, 16C, 16D, 16E, 16F, and 16G each formed of a silicon oxide film and silicon nitride films 17B, 17C, 17D, 17E, and 17F is formed on the SiN film 17A covering the transistor 15Tr on the silicon substrate 15.
In the case illustrated in FIG. 2, in the interlayer insulating film 16A, via patters 16aR of a material such as W are continuously formed in contact with the surface of the silicon substrate 15 in correspondence to the moisture resistant ring 12A, and via plugs 16a of a material such as W are formed in contact with silicide layers 15c and 15d covering diffusion regions 15a and 15b, respectively, of the transistor 15Tr in the circuit region 13.
Further, in the interlayer insulating film 16B, a Cu pattern 16bR is continuously formed in contact with the via patterns 16aR by a single damascene process in correspondence to the moisture resistant ring 12A, and Cu interconnection patterns 16b are formed in contact with the via plugs 16a also by a single damascene process in the circuit region 13.
Further, in the interlayer insulating film 16C, a Cu pattern 16cR is continuously formed in contact with the Cu pattern 16bR below by a single or dual damascene process in correspondence to the moisture resistant ring 12A, and Cu interconnection patterns 16c having via plugs are formed in contact with the Cu interconnection patterns 16b also by a single or dual damascene process in the circuit region 13.
Further, in the interlayer insulating film 16D, a Cu pattern 16dR is continuously formed in contact with the Cu pattern 16cR below by a single or dual damascene process in correspondence to the moisture resistant ring 12A, and Cu interconnection patterns 16d having via plugs are formed in contact with the Cu interconnection patterns 16c also by a single or dual damascene process in the circuit region 13.
Further, in the interlayer insulating film 16E, a Cu pattern 16eR is continuously formed in contact with a Cu pattern below (not graphically illustrated) by a dual damascene process in correspondence to the moisture resistant ring 12A, and Cu interconnection patterns 16e having via plugs are formed in contact with Cu interconnection patterns (not graphically illustrated) also by a dual damascene process in the circuit region 13.
Further, in the interlayer insulating film 16F, a Cu pattern 16fR is continuously formed in contact with the Cu pattern 16eR below by a dual damascene process in correspondence to the moisture resistant ring 12A, and Cu interconnection patterns 16f having via plugs are formed in contact with the Cu interconnection patterns 16e also by a dual damascene process in the circuit region 13.
Further, in the interlayer insulating film 16G, a W pattern 16gR is continuously formed in contact with the Cu pattern 16fR below by a damascene process in correspondence to the moisture resistant ring 12A, and a Cu via plug 16g is formed in contact with the corresponding Cu interconnection pattern 16f also by a damascene process in the circuit region 13.
Here, the Cu interconnection patterns 16b through 16f and the Cu patterns 16bR through 16fR are covered with a barrier metal film of Ta or the like, and the W via plugs 16a and 16g and the W patterns 16aR and 16gR are covered with a barrier film of TiN or the like.
Further, on the interlayer insulating film 16G, an Al pattern 18A sandwiched between adhesion films of a Ti/TiN structure is formed in contact with the W pattern 16gR in correspondence to the moisture resistant ring 12A, and a pad electrode 18B having a similar structure is formed on and in contact with the via plug 16g. 
Further, the Al pattern 18A and the pad electrode 18B are covered with a silicon oxide film 18 deposited by high-density plasma CVD on the interlayer insulating film 16G. Further, a passivation film 19 of a SiN film is formed on the silicon oxide film 18. An opening 19A is formed in the passivation film 19 and the silicon oxide film 18 so as to expose the pad electrode 18B.
According to the configuration of FIG. 2, scribing is performed with a dicing saw at the left side end in FIG. 2 as indicated by an arrow. The protection groove 14A illustrated above with reference to FIG. 1 is formed outside the moisture resistant ring 12A in order to block propagation of cracks at the time of scribing.
On the other hand, according to the semiconductor device 10 of the configuration of FIG. 2, its left side end in FIG. 2 is exposed to the atmosphere. Therefore, as illustrated in FIG. 3, moisture (H2O) enters the portions of the interlayer insulating films 16A through 16F outside the moisture resistant ring 12A, but the moisture resistant ring 12A prevents this moisture from entering the circuit region 13. Accordingly, there is a problem in that the moisture resistant ring 12A, on which a heavy workload is imposed, is susceptible to corrosion. If there is a defect in part of the moisture resistant ring 12A, moisture enters the semiconductor device 10 through the part. In FIG. 3, such a defect is in the Cu pattern 16cR of the moisture resistant ring 12A circled with a broken line.
This problem of the workload on the moisture resistant ring 12A is conspicuous particularly in the case of using low dielectric constant films of low density, or so-called Low-K films, as the interlayer insulating films 16A through 16F.
FIG. 4 is a diagram illustrating a semiconductor device that reduces such a workload on a moisture resistant ring according to the related art of the present invention. In FIG. 4, the same elements as those described above are referred to by the same reference numerals, and a description thereof is omitted.
Referring to FIG. 4, the protection groove part 14A is formed so deep as to reach the surface of the silicon substrate 15, and the SiN passivation film 19 is formed to continuously cover the surface of the protection groove part 14A.
As a result, the interlayer insulating films 16A through 16F and the interlayer insulating film 16G have their respective ends continuously covered with the SiN passivation film 19, so as to reduce a substantial workload on the moisture resistant ring 12A.
The following are examples of the related art of the present invention: Japanese Laid-open Patent Publication No. 2004-47575, Japanese Laid-open Patent Publication No. 2004-134450, Japanese Laid-open Patent Publication No. 2004-79596, Japanese Laid-open Patent Publication No. 2003-273043, Japanese Laid-open Patent Publication No. 2004-119468, Japanese Laid-open Patent Publication No. 2005-217411, Japanese Laid-open Patent Publication No. 2005-260059, Japanese Laid-open Patent Publication No. 2004-296904, and Japanese Laid-open Patent Publication No. 2006-114723.